The design complexity of integrated circuits (e.g., mobile radio frequency (RF) chips or transceivers) is complicated by added circuit functions to support communication enhancements. The design of these mobile RF transceivers may include the use of silicon-on-insulator technology. Silicon-on-insulator (SOI) technology replaces conventional semiconductor (e.g., silicon) substrates (e.g., wafers) with a layered silicon-insulator-silicon substrate to reduce parasitic device capacitance and improve performance.
The active devices on the SOI layer may include complementary metal oxide semiconductor (CMOS) transistors. RF switch devices of mobile RF transceivers may be fabricated using CMOS transistors on SOI substrates. Unfortunately, successful fabrication of transistors using SOI technology is complicated by a parasitic environment (e.g., parasitic capacitance). Parasitic capacitance may be caused by a proximity of an active device on the semiconductor layer and a semiconductor substrate supporting a buried oxide (BOX) layer in SOI devices.
Parasitic capacitance may also be caused by the interconnects to gates and source/drain regions of the CMOS transistors. This form of contact/interconnect-to-gate capacitance is caused by a proximity between back-end-of-line (BEOL) interconnects and/or middle-of-line (MOL) trench contacts/interconnects and the transistor gates as well as the transistor gate interconnects. This parasitic capacitance adversely affects the performance of CMOS devices, resulting in circuit delays and losses. This capacitance is especially problematic for RF switch devices.